Laboratoire de l'informatique du parallélisme; Bidault, Thierry; Guillon, Christophe; Bouchez, Florent; Rastello, Fabrice
(2004-04)
(eng) Instruction cache performance is one of the bottle-necks of processor performance. In this paper, we study the effects of procedure placement in memory on a direct-mapped instruction cache. These caches differ from ...